A novel characteristic curve for thermoelectric cooler application in realistic thermal circumstances: Theory and experiment

On the materials level, the performance of thermoelectric (TE) devices can be defined by the thermoelectric figure of merit (zT). This, however, does not provide a complete picture due to the complex interplay between electronic and thermal transport properties and the uncertain thermal impedance matching between external and internal thermal resistances in different realistic thermal circumstances. Appropriate design of individual material properties and geometry parameters considering the realistic thermal circumstance can greatly enhance the device-level performance of TE devices. In this work, we develop a framework to clarify such interactions in thermoelectric coolers (TEC) with a newly proposed q-h characteristic curve, which can be used to identify how a TEC design is of effectiveness for a specific realistic thermal circumstance. The effects of zT, the individual TE material properties (i.e., thermal conductivity k, electrical conductivity σ and Seebeck coefficient S) as well as the geometry parameters (i.e., pillar height and filling factor) on the q-h characteristic curve are theoretically and experimentally investigated, respectively. TEC modules with higher zT, short pillars and high filling factor show stronger capability to handle high heat flux load, especially for the cases with high heat dissipation coefficient at hot side. The thermal property (k) and electrical properties (σ and S) are responsible for the low heat flux load (e.g., wearable TEC) and high heat flux load (e.g., on-chip TEC cooling), respectively. For wearable TEC, increasing the internal thermal resistance can prevent the back flow heat, which can be achieved with tall pillars, low filling factor and optimizing zT towards lowering thermal conductivity k. For on-chip TEC cooling, reducing the Joule heating and increasing the thermoelectric effect become dominant factors in lowering the code-side temperature of TEC modules. This can be achieved with short pillars, high filling factor and optimizing zT towards increasing the power factor S2σ. This work provides significant insights into the complex interplay between material-level properties, device-level parameters and the external thermal circumstance in determining the performance of TEC devices. The results enable researchers to design optimal TEC devices for realistic applications with different boundary conditions.