Study of selective isotropic etching effects of Si1-xGex in gate-all-around nanosheet transistor process

Gate-all-around (GAA) nanosheet transistors are widely accepted for the mainstream technology towards 3nm technology node. The major strategy is to form nanosheet by using Si1-xGex/Si multilayer structures (MLS). Inner spacer formation is a critical step as it defines the gate length and isolates gate from source and drain. Selectively removing of SiGe layers determines the dimension of the inner spacer and impacts the transistor performance significantly. It requires precise process control in the lateral cavity etching and brings significant challenges to conventional etching manners. In our previous work, we achieved isotropic Si0.7Ge0.3 selective etching in SiGe/Si stack with high selectivity. However, the results were achieved on the single SiGe/Si stack in a relatively open area, when moving to dense patterns, the etching performance desires for further study. In this paper, we present our latest progress on isotropic etching by using ICP with mixed gas of CF4/O2/He on SiGe/Si stack periodic arrays. Loading effect and Si surface damage were observed. We reproduce these etching effects by developing an analytical model. This model is based on Monte-Carlo method and is capable of simulating the profile evolution of the lateral etching of SiGe/Si structures. The influence of etch time, pattern pitch and stack layer thickness on lateral etch results have been studied by simulation.