Low-Hardware Consumption, Resolution-Configurable Gray Code Oscillator Time-to-Digital Converters Implemented in 16 nm, 20 nm, and 28 nm FPGAs

This article presents a low-hardware consumption, resolution-configurable, automatically calibrating gray code oscillator time-to-digital converter (TDC) in Xilinx 16-nm UltraScale+, 20-nm UltraScale and 28-nm Virtex-7 field-programmable gate arrays (FPGAs). The proposed TDC utilizes look-up tables as delay elements and has several innovations: 1) a sampling matrix structure to improve the resolution, 2) a virtual bin calibration method (VBCM) to achieve configurable resolutions and automatic calibration, and 3) hardware implementation of the VBCM in standard FPGA devices. We implemented and evaluated a 16-channel TDC system in all three FPGAs. The UltraScale+ version achieved the best resolution (least significant bit, LSB) of 20.97 ps with 0.09 LSB averaged peak-to-peak differential nonlinearity (DNL _pk–pk ). The UltraScale and Virtex-7 versions achieved the best resolutions of 36.01 ps with 0.10 LSB averaged DNL _pk–pk and 34.84 ps with 0.08 LSB averaged DNL _pk–pk , respectively.