总谐波失真
脉冲宽度调制
逆变器
电压
控制理论(社会学)
失真(音乐)
电子工程
工程类
数学
计算机科学
电气工程
CMOS芯片
人工智能
放大器
控制(管理)
作者
Yuhang Zou,Li Zhang,Huizi Zhuge,Yan Xing,Zhongshu Zheng,Yiding Wu
标识
DOI:10.1109/iecon51785.2023.10312102
摘要
Neutral-point (NP) voltage imbalance causes severe alternating output current distortion in three-phase three-level inverters when conventional discontinuous PWM (DPWM) schemes are employed. Existing improved DPWM schemes can not achieve low total harmonic distortion (THD) and simple digital implementation simultaneously. In this paper, a pulse-width compensation (PWC) scheme is proposed to improve the THD performance of DPWM-based three-level inverters under unbalanced NP voltage conditions. By using the proposed PWC scheme, the pulse width of the bridge-leg voltage of the unclamped phases is compensated according to the NP voltage. As a result, the fundamental component of the bridge-leg voltage is not affected by the NP voltage, and the alternating output current distortion is improved. Finally, a 6-kW inverter prototype is built, and experimental results show that the proposed PWC scheme can achieve low THD and simpler digital implementation than the existing improved DPWM scheme.
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