A Study on SADP Film Stack Selection for Line Roughness Improvement in Planar 1Xnm NAND Flash

With planar NAND flash technology scaling down to reach 1xnm node, interference between cell has become the major factor for cycling and reliability degradation. Self-Aligned Double Patterning (SADP) approach has already been widely used to achieve the required complex structure of both AA and gate. Proper film stack selection can result in superior difference on physical structure and final performance. In this work, physical performance including CD bias, sidewall angle, line roughness and pitch walking are studied for different film stack selection. Further critical process tuning is also applied to optimize profile control and pattern loading by introducing extra process steps.