现场可编程门阵列
吞吐量
硬件加速
电阻抗断层成像
计算机科学
GSM演进的增强数据速率
计算机硬件
电阻抗
嵌入式系统
电气工程
工程类
人工智能
无线
电信
作者
Varun Tiwari,Mahmoud Meribout
标识
DOI:10.1109/jsen.2024.3447099
摘要
This article addresses the demands of high-resolution 2-D electrical impedance tomography (EIT) systems, which necessitate an increased number of electrodes and finer mesh structures compared to their traditional counterparts. These requirements lead to higher data acquisition and computational loads. Given the inherently inverse and ill-posed nature of EIT, achieving a high signal-to-noise ratio (SNR) and precision hardware acceleration is essential. This article introduces a field-programmable gate array (FPGA)-based data acquisition system equipped with a tunable single-frequency current source, achieving acquisition speeds exceeding 500 and 2400 frames per second (fps) for 32 and 16 electrodes, respectively, with a 500-kHz excitation signal frequency. Data processing and reconstruction utilize the latest embedded graphics processing unit (GPU), specifically NVIDIA Jetson Orin, leveraging multiple CUDA cores for parallel high-speed 2-D image reconstruction. Comparative evaluations of five algorithms, namely, linear back projection (LBP), Tikhonov (TK) regularization, one-step Gauss–Newton (GN), Landweber (LW), and iterative Tikhonov (ITK), show a speed gain of at least fourfold compared to traditional implementations on standard computers. Experimental results reveal that the proposed system can achieve over 2500 fps throughput for a 16-electrode setup with approximately 8192 mesh elements. This advancement opens new possibilities for high-speed imaging and large-scale 3-D EIT applications.
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