A Memory Optimized Architecture for Multi-Field Packet Classification (Brief Announcement)

The high-performance hardware architectures for multi-field packet classification have been studied over the past decade. Although many FPGA-based solutions can achieve very high throughput, the limited FPGA resources severely hinders the scalability of the rulesets or matching fields. To address this issue, we present a parallel architecture named Wildcard-removed Two-dimensional Pipeline (WeeTP) to save memory usage of wildcards and reduce logic resources. WeeTP uses the Maximum Wildcard Overlap (MWO) algorithm to maximize the compression percentage by rearranging the ruleset. We implement and evaluate WeeTP on an Intel STRATIX V FPGA. Experimental results show that our approach can save 37% and 41% memory consumption on average for real 5-tuple rules and OpenFlow rules, respectively.