Analysis of Control-Delay Reduction for the Improvement of UPS Voltage-Loop Bandwidth

This paper investigates the effects of control-delay minimization in the dynamic performance of the output stage of uninterruptible power supplies (UPSs) by shifting the sampling time of inductor current and output voltage toward the duty-cycle update instant. This paper shows how a small shift of the output-voltage sampling can significantly increase the UPS voltage-loop bandwidth while keeping the same stability margin. Instead, less contribution comes from the delay minimization of the inductor-current sampling, so that current-ripple cancellation techniques are not needed. A detailed model based on the modified $Z$ -transform, which accounts for different time delays in multiloop control, is proposed. The effectiveness of the proposed analysis is demonstrated by simulation and experimental results on a typical industrial three-phase/three-phase 8-kHz 30-$\hbox{kVA}$ UPS prototype. By using two control designs based on the same phase margin, the output-voltage total harmonic distortion with the normalized distorting load is reduced from 6.8% to 5.7%, using a delay of the output voltage sampling equal to 25 $\mu\hbox{s}$.