Accurate determination of threshold voltage shift during negative gate bias stress in 4H-SiC MOSFETs by fast on-the-fly method

Abstract The threshold voltage shift in NO-annealed 4H-SiC MOSFETs during negative gate bias stress was investigated with a fast on-the-fly method for p-channel devices while considering the stress–time dependence of the slope of the drain current–gate voltage characteristics. With the proposed method, the threshold voltage shift was accurately measured over a wide time range from hundreds of nanoseconds. The negative threshold voltage shift exhibited power-law time dependence at room temperature and logarithmic time dependence at 423 K, suggesting that interface trap generation is observable at room temperature and thermally-assisted hole trapping in SiO 2 dominates at high temperatures.