Optimization of BEOL Capacitor Matching in Charge Redistribution DACs for Precision and High-Speed ADCs

Capacitor matching in large digital to analog converter (DAC) arrays is a key limitation for the performance of precision successive approximation register (SAR) analog to digital converter (ADC) linearity, signal to noise ratio (SNR) and signal to noise and distortion ratio (SNDR). Costly techniques such as noise-shaping, calibration and dynamic element matching techniques are often used to ensure the required linearity. Currently available matching data for capacitor models are not sufficient for the estimation of the performance of capacitive-DACs having a dynamic range above 5 bit or in excess of 32 unit elements. To address these limitations, an in-depth analysis of the impact of the geometry of lateral metal-oxide-metal (MOM) capacitors on matching errors is presented in this paper, based on the study of a 256-element charge-redistribution DAC. The impacts of capacitor finger length, width, and spacing are individually considered and characterised over a sample of 96 die, from 3 different wafers in a 40nm CMOS process. The systematic and random mismatch relationships are decorrelated and considered in isolation. Observed trends and dependencies are presented, and used for the optimisation of dimensioning and layout in a capacitor structure found to achieve >4x improvement compared with typical standard-library cell arrays. The optimised and parameterised DAC arrays are employed within a scaled-reference SAR ADC, achieving 99.3 dB SNR figure (uncalibrated) due to the improved structures.