A 7-bit 1.15-GS/s 2.6-bit/Cycle Asynchronous SAR ADC Using Comparator Decision Skip Technique With Background Offset Calibration

This article presents a 7-bit, 1.15-GS/s, 2.6-bit/cycle asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) that incorporates a comparator decision skip technique and background offset calibration. The ADC comparison time is fundamentally limited by comparator metastability. The proposed decision skip technique ensures correct operation even in the presence of metastability, thereby reducing comparison time and improving conversion speed. Conventional background offset calibration is performed concurrently with 1-bit conversions. In contrast, the proposed alternative CDAC voltage generation method performs calibration during 2-bit conversions, eliminating the need for additional calibration cycles. The prototype ADC was fabricated in a 28-nm CMOS process technology. Measurement results show a signal-to-noise-and-distortion ratio (SNDR) of 39.39 dB and a spurious-free dynamic range (SFDR) of 54.02 dB at the Nyquist frequency. The ADC consumes 3.8 mW at a 1.15-GS/s sampling rate and achieves a Walden figure of merit (FoMw) of 41.9 fJ/conversion step.