Characterisation of the pFREYA16 ASIC for low-noise ptychography applications

The pFREYA16 ASIC is an 8 x 2 prototype pixellated matrix developed to comply with the stringent requirements on both noise performance and frame acquisition speed imposed by recent x-ray ptychography applications. Namely, each pixel in the matrix was designed focusing mainly on single photon detection at 5 keV, 9 keV and 25 keV photon energies, with an equivalent noise charge of 250 e-rms obtained in post-layout simulations in the nominal case, and 1 MHz conversion rate, comprising integration by means of a charge sensitive amplifier, signal shaping through an RC-CR stage, discrimination of interesting signals and analog to digital conversion. The whole chain is integrated in each pixel. pFREYA16 is the first step to validate the architecture of a future 128-by-128 matrix. The channel power consumption is 220 μW in post-layout simulations in the nominal case and the elementary cell area occupation is 150 μm x 150 μm. The ASIC, together with a test structure matrix, has been submitted in Q4 2022, is currently in the assembly house for bonding and will be received by the end of Q2 2023. This summary will focus on the pFREYA16 design and development, while the conference presentation will also showcase the results from the characterisation of the produced chips.