A Capacitor-Coupled Offset-Canceled Sense Amplifier for DRAMs With Hidden Offset-Cancellation Time and Cross-Coupled Pre-Sensing

As the dynamic random-access memory (DRAM) process is being scaled down, the sensing margin of the bit-line sense amplifier (BLSA) is decreasing. This leads to sensing failure due to the offset and long sensing time of the BLSA. To address this issue, various offset compensation methods and technologies that reduce sensing time have been proposed. However, these technologies still exhibit sensing failure due to long sensing times in low-power and large-capacity memory with low supply voltage and high $C_{BLT}/C_{Cell}$ ratio. In addition, previous BLSAs require additional offset compensation time, which further increases the sensing time. A hidden-offset cancellation time and cross-coupled pre-sensing capacitor-coupled offset-canceled sense amplifier (HCP_COSA) are proposed to address these problems. To reduce the sensing time, the separate offset cancellation (OC) cycle is eliminated by performing OC for the cross-coupled inverter and charge-sharing simultaneously. In addition, the cross-coupled inverter operation is used in the pre-sensing phase to further amplify the reference bit line (BLB) voltage with the opposite polarity of the read-out signal, thereby improving both sensing margin and time. The proposed HCP_COSA achieves up to 18.5% faster sensing time at a supply voltage of 0.9 V by increasing the difference between the bit line (BLT) and the BLB by 2.55-3.76 times before starting the main sensing (MS) phase, compared with the previous works. In addition, the proposed architecture increases the number of word lines that can be sensed by up to 33.3% and achieves a sensing yield of 100% even at a low supply voltage of 0.65 V.