A novel 1.2 kV 4 H-SiC charge sheet superjunction trench MOSFET: modeling, process design, and practicability

Abstract This work presents a novel 4 H-SiC charge sheet superjunction (CSSJ) trench metal-oxide-semiconductor field-effect transistor (MOSFET) in which a CSSJ-based drift layer is integrated into a conventional trench MOSFET. Analytical modeling, design, and optimization of the proposed device are presented for a target breakdown voltage, V BR , of 1.2 kV. The design considers a typical worst-case charge imbalance of up to 20% due to inevitable process variations during fabrication. Our solution predicts that, by using the CSSJ-based drift layer, the specific on resistance, R ONSP , of the device can be several times lower than devices with conventional drift layers for the same rated voltage. Consequently, the proposed device predicts one of the highest figure of merit (FOM= V BR 2 / R ONSP ) of 3094 MW cm −2 for 4 H-SiC MOSFETs. We also outline the potential fabrication steps validated by a well-calibrated process simulation. Rounded trench corners and a p-shielding region below the gate trench are used for mitigating early device failure due to gate oxide breakdown. For the designed device, the simulated V BR is 1.14 kV, the R ONSP is 0.42 mΩ.cm 2 , and the peak oxide electric field at breakdown is 2.9 MV cm −1 . Furthermore, we demonstrate a process simulation-predicted optimized charge of ∼−6 × 10 12 cm −2 at the Al 2 O 3 /SiO 2 interface on fabricated planar metal-oxide-semiconductor (MOS) test structures using capacitance-voltage (CV) measurements. This should build strong motivation for complete realization of the device.