Thermal Management Challenges in 2.5D and 3D Chiplet Integration: A Review on Architecture–Cooling Co-Design

The increasing power density of 2.5D and 3D chiplets imposes severe thermal constraints that have a direct impact on the performance and long-term reliability of high-performance computing systems. Stacked and laterally integrated dies, which generate hundreds of watts per package, create localized hotspots and inconsistent temperature fields, major obstacles to scalable heterogeneous integration. Research efforts have addressed these challenges by finite element and compact heat modeling, thermal interface material optimization (TIM), and advanced cooling solutions such as micro-channel liquid cooling and cold racks. While these approaches provide valuable insights, most remain case-specific, focusing on isolated packages or single design variables, and lack a general methodology for assessing thermal feasibility at an early stage. This review consolidates and critically analyzes contributions to thermal modeling at the package level, interposer thermal spreading, thermal characterization of TIMs, and the development of cooling technologies. A comparative review of published studies indicates a consistent threshold: 2.5D stacks are viable under air cooling at approximately 300 W, whereas 3D stacks require liquid or hybrid cooling in conjunction with high-performance thermal interface materials at about 350 W. The investigations identify interposer conductivity, thermal interface material thickness, and hotspot power distribution as the primary sensitivity elements. This study explores Thermal Feasibility Maps (TFMs), defined as multidimensional charts parameterized by architecture, cooling regime, and material stack. TFMs provide a systematic framework for comparing design trade-offs and support architecture cooling co-design in advanced chiplet systems.