Defect conscious approaches in EUV patterning

The aim of this study is to lessen the number of defects by the simultaneous analyses of detection result via the lithography process and etch transfer performance. While defect requirements aren't as stringent for memory devices, logic devices must be defect-free. Currently, a defect which comes from the process or material can only be detected by top-down inspection approach, however, it is difficult to detect a defect such as underlying hole. To develop 5-nm logic node, a hole pattern 15 nm or smaller is required. Identification of failure at the bottom of the hole becomes more challenging. Nevertheless, the process window margin by the amount of dose/focus is not fully explored to find the defect occurrence tendency. So far, there are reported analyses on the scaling of pattern and pitches. In this paper, we report the process margin spotted on the amount of dose and the focus depth and the comprehensive process window including a view of defect-free.