Chip-package-board reliability of System-in-Package using laminate chip embedding technology based on Cu leadframe

We investigated a System-in-Package (SiP) technology using laminate chip embedding based on a copper leadframe. This SiP technology included different Si-based transistor technologies. We tested the reliability of three types of chip embedding packages: a single-chip package (SCP) with an embedded MOSFET test chip for basic understanding, and two SiPs: a multi-chip package (MCP) with a DC/DC converter for industrial applications and a SiP for lighting applications. In order to better represent specific field stresses for the target applications we developed and investigated new test methods for laminate based packages. In this paper we report the design, the implementation and the results of those new methods and discuss their benefits and validity. We conducted conventional test methods like temperature shock tests for comparison. The results of all these tests demonstrate a very good reliability of the chip embedding packages. We also investigated early damages inside the packages using failure analysis techniques like cross sectioning. The cooperation of partners among the value chain resulted in a coherent understanding of chip-package-board material aspects and design for reliability.