光电子学
材料科学
晶体管
电阻式触摸屏
等效串联电阻
栅氧化层
和大门
电镀
金属浇口
功率(物理)
逻辑门
功率密度
电气工程
纳米技术
电压
物理
图层(电子)
工程类
量子力学
作者
Hossein Yazdani,Andreas Thies,Paul Stützle,Olof Bengtsson,Oliver Hilt,W. Heinrich,Joachim Wuerfl
标识
DOI:10.1088/1361-6641/ad1b16
摘要
Abstract This paper presents a novel approach for reducing the gate resistance ( R g ) of K and Ka-band GaN HFETs with 150 nm gate length through a new gate metallization technique. The method involves increasing the gate cross-section via galvanic metallization using FBH’s Ir-sputter gate technology, which allows an increase in gate metal thickness from the current 0.4 μ m to approximately 1.0 μ m for the transistors under investigation. This optimization leads to a substantial 50% reduction in gate series resistance, resulting in significant improvements in the RF performance. Specifically, the devices achieve 20% higher output power density and 10% better power-added efficiency at 20 GHz and V ds = 20 V. The decreased gate resistance enables new degrees of freedom in design, such as longer gate fingers and/or shorter gate lengths, for more efficient power cells operating in this frequency range.
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