Clock Period-Jitter Measurement With Low-Noise Runtime Calibration for Chips in FinFET CMOS

Process migration from bulk to FinFET CMOS pronounces die-to-die and within-die process variations. Runtime variations get severe as the clock frequency goes higher. Facing these two issues makes on-chip clock period-jitter measurement with a high resolution very difficult. In this work, we propose low-noise runtime resolution calibration and jitter measurement for designing a period-jitter measurement circuit, called a period-jitter sensor (PJS), in the face of higher variations imposed on the PJS. Essential design techniques include edge-triggered and symmetrical architecture and circuits for noise reduction, variation resiliency, and power saving. As a test vehicle, we have designed a PJS to measure the clock quality of an LPDDR4-4266 physical layer with the clock cycle time and the maximum period jitter specified to be 468.82ps and $\pm$ 30ps, respectively. The design specifies the minimum runtime resolution to be better than 1.0 ps. Measurement results show that the 0.0192mm $^{2}$ 2.133GHz PJS in 14nm FinFET CMOS achieves a sub-ps resolution in runtime and only consumes around 1mW across all PVT conditions, making multiple embedding of the PJS in a complex SoC feasible.