Analytical modeling and experimental evaluation of interconnect parasitic inductance on MOSFET switching characteristics

The impact of interconnection parasitic inductance on MOSFET switching characteristics is modeled analytically and evaluated experimentally. Closed-form analytical equations are derived to evaluate switching characteristics due to common source inductance and switching loop inductance. Assuming an identical total parasitic inductance, a MOSFET with higher common source inductance has higher switching energy loss but lower overshoot voltage than a MOSFET with higher switching loop inductance. The tradeoffs between switching loss and signal overshoot and oscillation are included in design criteria for optimizing switching performance of packaged power electronics. The experimental results are in good agreement with the analytical modeling.