拓扑(电路)
计算机科学
物理
算法
电子工程
功率(物理)
作者
Ching-Yuan Yang,Chih-Hsiang Chang,Wen-Ger Wong
出处
期刊:IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
[Institute of Electronics, Information and Communications Engineers]
日期:2008-02-01
卷期号:91 (2): 497-503
被引量:2
标识
DOI:10.1093/ietfec/e91-a.2.497
摘要
A high-speed triangular-modulated spread-spectrum clock generator using a fractional phase-locked loop is presented. The fractional division is implemented by a nested fractional topology, which is constructed from a dual-modulus divide-by-(N–1/16)/N divider to divide the VCO outputs as a first division period and a fractional control circuit to establish a second division period to cause the overall fractional division. The dual-modulus divider introduces a delay-locked-loop network to achieve phase compensation. Operating at the frequency of 3.2 GHz, the measured peak power reduction is around 16 dB for a deviation of 0.37% and a frequency modulation of 33 kHz. The circuit occupies 1.4 × 1.4 mm2 in a 0.18-μm CMOS process and consumes 52 mW.
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