Development of Low‐Temperature Doping Process in CdSe‐Nanocrystal Thin Films for Flexible Electronic and Optoelectronic Devices

Abstract An effective surface‐doping strategy for CdSe nanocrystals (NCs) by examining the size‐dependency of the doping behavior is introduced. A CdSe NC thin‐film transistor (TFT) is fabricated via a doping process with InCl 3 treatment followed by an annealing process. Spectroscopic and electronic device characterization reveal that smaller NCs are more effectively doped than larger NCs at all annealing temperatures. This is attributed to the larger specific surface area, where the dopant can be more readily coordinated. The degenerate behavior of a 3.3 nm CdSe‐NC TFT appears at a lower temperature than that of larger NC TFTs. High electron mobility and on‐to‐off current ratio of 1.79 cm 2 Vs −1 and 5.2 × 10 5 , respectively are achieved, in a low‐temperature annealing process (150 °C) with 3.3 nm CdSe NCs. This facilitates the fabrication of a flexible CdSe‐NC TFT, which is demonstrated on a polyethylene terephthalate substrate with an Al 2 O 3 dielectric layer using atomic layer deposition. The flexible 3.3 nm CdSe‐NC TFT is successfully fabricated even at 150 °C, with a high on‐to‐off current ratio and low hysteresis at a low operation voltage, which is impossible for larger CdSe‐NC TFTs.