On the Understanding of pMOS NBTI Degradation in Advance Nodes: Characterization, Modeling, and Exploration on the Physical Origin of Defects

A complete separation flow for different types of traps, including the separation of energy levels (ETs) and the separation of charging kinetics, making different traps can be modeled and characterized separately by simple experiments. Industrial-grade 7 nm pFinFETs under negative bias temperature instability (NBTI) stress condition is chosen for the demonstration. Four types of traps are identified, including oxide trap Type-A located in the interfacial layer (IL) layer, oxide trap Type-B (B1 and B2) located in the HK layer, and interface trap Type-C located at Si/IL interface. Type-A trap belongs to a preexisting trap which can be well described by the two-state non-radiative multiphonon (NMP) theory and may originate from Vo in SiO2. Types-B1 and Type-B2 traps originate from Ni and Hi respectively, and can be described by incorporating the activation state into the two-state NMP theory. Type-C is located at Si/IL interface and follows the classical power law relationship with the time exponent of 0.17, which may be caused by the breakage of the Si-H bonds due to the reaction with atomic H from either the substrate or the gate. By modeling each type of trap respectively, a unified aging prediction framework was proposed and its long-term predictive capability was experimentally verified under various working conditions. The contribution of each trap to degradation is also discussed, which is helpful to the Design-Technology co-optimization (DTCO) in advanced nodes.