Performance limit of one-dimensional SbSI nanowire transistors

The gate-length ( L g , L g = 5, 3, 1 nm) n- and p-type gate-all-around SbSI FETs having a suitable underlap can fulfill the power dissipation, delay time, and on-state current for the 2028 prerequisites for the HP and LP requirement of the ITRS of 2013.