Bumpless WOW stacking for large-scale 3D integration
作者
Takayuki Ohba
出处
期刊:IEEE International Conference on Solid-State and Integrated Circuit Technology日期:2010-11-01卷期号:: 70-73被引量:5
标识
DOI:10.1109/icsict.2010.5667847
摘要
Wafer-scale three-dimensional (3D) technologies beyond post-scaling, known as Wafer-on-Wafer (WOW), have been developed for high-density integration. WOW consists of four technology modules: wafer thinning, stacking, through-silicon-via (TSV) interconnects without bump electrode pads, and packaging. All modules are carried out at the wafer scale. No degradation for advanced 35-nm SRAM logic and FRAM devices was observed with ultra-thinning below 10-μm for 300-mm and 200-mm wafers.