An Ultra-Low-Noise LDO Regulator in 65 nm for Analog Front-End ASICs in Cryogenic Environment

Low dropout (LDO) voltage regulators, which provide a clean supply for analog and mixed-signal systems, are essential to low-noise front-end electronics in high energy physics experiments and beyond. This paper analyzes the noise sources in an LDO where the input referred noise of the error amplifier is the dominant noise source. Implemented in 65 nm technology, the LDO presented here regulates a noisy 1.5 V supply and outputs a stable and low-noise nominal 1.175 V voltage with load current ranging from a few milliamp up to 150 mA. The design achieves higher than 75% power efficiency at both room and cryogenic temperatures at maximum load, with more than 40 dB power supply rejection up to 400 kHz. The simulated RMS noise from 10 Hz to 100 kHz is less than 2 μV at room temperature and less than 1 μV at 77 K. The regulator requires an external capacitance of 50 μF for stability. A number of next-generation detectors can greatly benefit from having this voltage regulator directly integrated in the front-end application-specific integrated circuits (FE-ASICs) working at room and cryogenic temperatures.