Lithography-defect-driven source-mask optimization solution for full-chip optical proximity correction

In the domain of computational lithography, the performance of an optimized imaging solution is usually qualified with a full-chip posted-optical-proximity-correction lithography printing check to ensure the printing is defect free before committed for mask writing. It is thus highly preferable for the optimization process itself to be driven by the same defect detection mechanism towards a defect-free solution. On the other hand, the huge data size of chip layout poses great challenge to such optimization process, in terms of runtime and data storage. A gradient-based optimization scheme thus becomes necessary. To date, no successful engineering tool is capable of accommodating these two requirements at the same time. We demonstrate the technology of defect-driven gradient-based optimization to achieve a defect-free solution within practical runtime specification, using ASML’s computational lithography product Tachyon SMO.