Sub-10 nm two-dimensional transistors: Theory and experiment

Presently Si-based field-effect transistors (FETs) are approaching their physical limit, and further scaling their gate length down to the sub-10 nm region is becoming extremely difficult. Benefitting from the atomic-scale thickness and dangling-bond-free flat surface, two-dimensional semiconductors (2DSCs) have good electrostatics and carrier transportability. The FETs based on the 2DSC channel have the potential to scale the FETs’ gate length down to the sub-10 nm region while avoiding apparent degradation of the device performance. In this review, we introduce the recent experimental and ab initio quantum transport simulation progress in the 2D FETs with a gate length less than 10 nm. Remarkably, in the extremely optimistic condition, many 2D FETs (i.e phosphorene, silicane, arsenene, tellurene, WSe2, InSe, Bi2O2Se, GeSe, etc.) show excellent device performance for the high performance and/or low power applications and indeed can extend Moore’s law down to 1∼2-nm gate length in terms of the ab initio quantum transport simulation. The sub-10 nm 2D tunneling FETs are predicted to generally have smaller energy-delay products compared with the 2D metal–oxide–semiconductor FETs and appear more competitive for the low power application. The carrier effective mass plays a key role in determining the device performance. Via negative capacitance techniques, the device performance can be further improved. Finally, we outline the challenges and outlook on the future development directions in the sub-10 nm 2D FETs.