A physics-based compact model of ferroelectric tunnel junction for memory and logic design

Ferroelectric tunnel junction (FTJ) is able to store non-volatile data in the spontaneous polarization direction of ferroelectric tunnel barrier. Recent progress has demonstrated its great potential to build up the next generation non-volatile memory and logic (NVM and NVL) thanks to the high OFF/ON resistance ratio, fast operation speed, low write power, non-destructive readout and so on. In this paper, we present the first physics-based compact model for Co/BTO/LSMO FTJ nanopillar, which was reported experimentally to exhibit excellent NVM performance. This model integrates related physical models of tunnel resistance, static switching voltage and dynamic switching delay. Its accuracy is shown by the good agreement between numerical model simulation and experimental measurements. This compact model has been developed in Verilog-A language and validated by single-cell simulation on Cadence Virtuoso Platform. Hybrid simulations based on 40 nm-technology node of FTJ memory arrays and non-volatile full adder were performed to demonstrate the efficiency of our compact model for the simulation and analysis of CMOS/FTJ integrated circuits.