锁相环
控制理论(社会学)
带宽(计算)
谐波
同步(交流)
电子工程
频率网格
自动频率控制
计算机科学
工程类
电压
抖动
控制(管理)
计算机网络
电信
频道(广播)
电气工程
人工智能
作者
Parag Kanjiya,Vinod Khadkikar,Mohamed Shawky El Moursi
出处
期刊:IEEE Transactions on Power Electronics
[Institute of Electrical and Electronics Engineers]
日期:2016-03-01
卷期号:31 (3): 2550-2561
被引量:68
标识
DOI:10.1109/tpel.2015.2435706
摘要
The synchronous reference frame phase-locked loop (SRF-PLL) is a widely used synchronization technique in power electronics and power systems applications due to its ease of implementation and robust performance. The conventional SRF-PLL is a type-2 control system due to the use of proportional-integral controller as loop filter. With higher bandwidth design, it can achieve fast detection of frequency and phase under ideal grid conditions. However, its bandwidth should be sufficiently lowered to obtain proper disturbance rejection under unbalanced and distorted grid conditions. This results in a slower detection speed. Recently, several advanced PLLs with pre/in-loop filtering stage have been proposed to improve the detection speed. A major challenge with the PLLs is how to further improve their dynamic performance without compromising the disturbance rejection capability and stability. To resolve this issue, in this paper, a novel type-1 frequency-locked loop (FLL) is proposed. The disturbance rejection capability of the proposed FLL is improved using a modified structure low-pass filter with selective harmonics filtering ability. As the proposed FLL is type-1 control system, it achieves better dynamic performance with higher stability margins. The effectiveness of the proposed FLL is confirmed through experimental results and comparison with advanced type-2 PLLs.
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