计算机科学
瓶颈
现场可编程门阵列
查阅表格
包转发
可扩展性
专用集成电路
隐藏物
路由表
网络数据包
吞吐量
嵌入式系统
路由器
网络处理器
计算机网络
操作系统
路由协议
无线
作者
Benjamin Wolff,Bachir Fradj,N. Belanger,Yvon Savaria
标识
DOI:10.1109/mwscas.2018.8623871
摘要
Increasing throughput requirements for Internet routers and growing routing table sizes have emphasized the need for fast and scalable packet forwarding systems. This paper presents a hardware cache-based IPv6 lookup system. Our goal is to study how much performance can be achieved with a lookup system that is implemented by modifying a processor cache. We show by prototyping our system on an FPGA board that our solution provides efficient IPv6 packet forwarding. In particular, the solution’s hardware complexity grows only linearly with table size. Our basic FPGA implementation can support a 1Gb link for minimum sized packets, and an improved implementation, discussed in this paper, could improve this throughput by an order of magnitude. Finally, an ASIC implementation would support 100Gb of bandwidth if there is no other bottleneck in the system.
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