Use of symbolic performance models in layout-inclusive RF low noise amplifier synthesis

We present a layout-in-loop synthesis method for radio-frequency LNAs, which uses symbolic performance models (SPMs), parameterized layout generator and high-frequency extraction techniques in the synthesis loop. The primary focus of this work is on performance estimation using efficient SPMs and development of techniques to include layout parasitics symbolically into the SPMs before the start of synthesis. SPMs for noise figure and distortion parameters are obtained using repetitive and weakly nonlinear symbolic analysis and are stored as pre-compiled element coefficient diagrams (ECDs). Speedy layout generation is achieved by using parameterized procedural layout generators and full parasitic extraction is done by using multiple extractors. Quasi-static extraction is used to obtain the critical parasitic effects of interconnects and on-chip inductors. The proposed methodology is used for the synthesis of low noise amplifiers (LNAs).