Potential-driven model for charge transfer efficiency in CCD-on-CMOS image sensors: addressing traps and nanogap potential wells

Abstract Although manufacturing charge-coupled devices (CCDs) on complementary metal–oxide–semiconductor (CMOS) processes enhances device integration and reduces power consumption, it introduces process features like thin oxide layers and nanoscale gate gaps. Specifically, thinned oxides cause gate oxide capacitance and relaxation time to increase beyond the traditional capacitive model limit, invalidating it. Concurrently, nanometer-scale gaps transform potential distributions from barriers to wells, causing traditional gap models to fail. These combined effects make existing CCD charge transfer efficiency (CTE) models inadequate for CCD on CMOS technology (CCD-on-CMOS) pixels. To address these limitations, this paper proposes a potential-driven CTE model tailored for CCD-on-CMOS pixels. This model solves the Poisson equation based on the depletion approximation to obtain potential distributions, incorporates N-well process parameters into a trap dynamics model, and quantifies the impact of gap width on carrier loss/delay by accurately computing the potential within nanoscale gaps. Validation demonstrates over 95.0% agreement with technology computer-aided design simulations. This model facilitates efficient CTE parameter analysis for CCD-on-CMOS devices, providing theoretical support for relevant CMOS process selection.