Analysis of the Induced Stresses in Silicon During Thermcompression Cu-Cu Bonding of Cu-Through-Vias in 3D-SIC Architecture

A new approach to 3D stacking of chips is being developed at IMEC and is called 3D-stacked IC (3D-SIC). In this approach, interconnection between strata is achieved by thermo-compression bonding of Cu-vias to a Cu-landing pad. In this paper we use finite element methods to study the influence of the resultant induced stresses in silicon as a result of CTE mismatch between silicon and copper and that also caused by the applied thermo-compression bonding force. Bonding temperature is found to be the main cause of induced stresses during thermo-compression bonding. The induced stresses decreased with a decrease in the silicon thickness. The keep-away-zone of the transistors from the influence of stresses from the Cu-vias is found to be dependent on the diameter of the Cu-via and the doping concentration of the transistors.