Adopting a Multi-issue, Out-of-order RISC-V Core Cluster in a Complex Modern System-on-Chip

The increasing need for powerful, yet power efficient SoCs has driven the VLSI industry towards extremely complex application processors while maintaining control over rigorous power saving schemes. A major change in processor technology was triggered by the introduction of RISC cores in early 1980s, which were extremely efficient, compared to the dominant CISC architecture at the time. RISC based computers were simpler, faster and power efficient compared to CISC processors. Majority of modern System-on-Chips (SoC) in mobile and automotive industry are driven by RISC based CPUs. The cost involved in the usage of advances licensed RISC processors has pushed the industry and academics towards open source hardware design. Adopting RISC-V enables the design of specialized processors for efficient handling of target applications, through a flexible, scalable and highly customized processor architecture. In this research, we analyze the feasibility of adopting RISC-V processors in a complex heterogeneous multi-master SoC by replacing ARM based CPU cluster with a RISC-V processor cluster while retaining the existing ARM based debug architecture. The RISC-V processor used is a 64-bit multi-issue, out of order, pipelined processor capable of high performance with low power consumption. We outline the difficulties, drawbacks, and advantages of working with RISC-V from design and verification perspectives, serving as a reference for engineers looking to adopt such systems in their designs. We also highlight and discuss the performance metrics observed between the two SoCs.