抖动
电子工程
均衡器
计算机科学
误码率
延迟(音频)
数字信号处理
电气工程
电信
工程类
解码方法
频道(广播)
作者
Haidang Lin,Charlie Boecker,Masum Hossain,Shankar Tangirala,Roxanne Vu,Socrates D. Vamvakos,Eric Groen,Simon Li,Prashant Choudhary,Nanyan Wang,Masumi Shibata,Hossein Taghavi,Marcus van Ierssel,AdilHussain Maniyar,Adam Wodkowski,Kulwant Brar,Nam Thành Nguyễn,Shaishav Desai
出处
期刊:IEEE Journal of Solid-state Circuits
[Institute of Electrical and Electronics Engineers]
日期:2021-04-01
卷期号:56 (4): 1265-1277
被引量:12
标识
DOI:10.1109/jssc.2021.3051109
摘要
This article describes a 4 × 112 Gb/s digital receiver targeting long-reach (LR) channels. An SNR optimized approach is presented, which relaxes the ADC resolution requirement and the number of FFE taps without sacrificing BER. The discrete-time front end overcomes gain-BW limitations to provide 10+ dB gain at 28 GHz. A 56-GS/s ADC then converts the signal to 6-b digital consuming only 195 mW. The following DFE-FFE-based digital equalizer is capable of compensating 36-dB loss achieving a BER of 2e-5. Furthermore, TDC and ISI filter-based low-latency timing recovery meet jitter tolerance specs over a wide range of data rates from 10 to 112 Gb/s, including 28-Gb/s NRZ. The overall receiver consumes 338 mW with 3.18-pJ/bit energy efficiency.
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