Pattern Centric Machine Learning Approach to Uncover Process Defects During Wafer Inspection and Review

The adoption of advanced reticle enhancement techniques has allowed patterning of smallest features in semiconductor manufacturing. Though the multitude the wafer processes have created a challenge for the existing modeling techniques even in the DUV (Deep Ultraviolet) patterning. Individual process owners strive to optimize their modules based on the data that is available within their purview. The co-ownership of chip yield is now driving the design process technology co-optimization. There has been a learning that layout pattern can serve as a common index to capture the response functions from multiple wafer processes [1], [2]. This requires identification of consequential patterns in the full chip layout and preserving this comprehensive design information throughout the fabrication life cycle. The big data thus collected at every sequential process step enables Pattern Centric Machine Learning that can be utilized in the optimization of each process [3], [4]. In this work we report a use case where PCML approach was utilized in uncovering the process defects by feeding in the process control systems. This approach enabled detection of new pattern defects with optical wafer inspection that is normally used for process monitoring.