Research and Improvement Of Metal Residues in High-K Metal Gate Process Based on CMP Process

In the gate last process, also known as replacement metal gate (RMG), amorphous silicon in the dummy gate should be removed first, then work function metal and metal gate should be filled. This process requires chemical mechanical planarization (CMP) method, which mainly includes inter-layer dielectric level zero (ILD0) and metal gate (MG) CMP, to accurately control the surface planarization of the filled Poly and metal surfaces. Both ILD0 and MG CMP have high control requirements for uniformity. If the remove amount of ILD0 CMP is insufficient, there will be residue defect of amorphous silicon, which will affect the filling of high-K metal gate. With insufficient MG CMP grinding, metal residues defect may occur. These problems are usually critical that lead to serious deviations in the yield of manufactured goods. In this paper, a optimization condition for ILD0 CMP and MG CMP is described. The experimental results show that the optimization method can effectively avoid the metal residues defect generation and improve the product yield.