Development and Research of a Deep Anisotropic Process for the Polysilicon Gates Implementation Using the ICP-RF System

The main task in the development of polysilicon anisotropic etching at the plant using Pseudo Bosch Process was to study the possibility of etching polysilicon gates. In this process, the following requirements for the output parameters are important: the etching profile of polysilicon should be vertical, i.e. the angle between the polysilicon wall and the substrate is close to 90°; there should be no undercutting under the photoresist mask, gate dielectric selectivity is above 3. Special requirements are also imposed on the purity of the etched surface, i.e. the process must be defect-free. The last requirement in the above list, the defect-free process, is not always possible to implement on conventional PCE plants with capacitive discharge systems. The most common etching method involves the use of an SF ₆ + CCl ₄ gas mixture. The CCl ₄ additive makes it possible to obtain an anisotropic profile due to the polymerization of the sidewalls of polysilicon, but it also leads to a very strong dependence on the quality of the etched film and photoresist mask. As a result of this work, in accordance with the conditions described above the etching process that allows us to realize in ICP-RF systems reactor using an SF ₆ + C ₄ F ₈ mixture was developed. The gas mixture of SF ₆ and C ₄ F ₈ in an optimized process has a ratio of 1:3 to provide high anisotropy without etching rate decrease, the bias power and the ICP power are 10 W and 450 W respectively. The process time is 234 s. Using an optimized process, it is possible to achieve a sidewall inclination angle of about 90° and an etching rate up to 1113 Å/min while maintaining the etching rate irregularity of about 2.6%. SiO ₂ selectivity close to 12 and photoresist mask selectivity is above 7.