A Calibration-Free Fractional-N Analog PLL With Negligible DSM Quantization Noise

An analog fractional-N phase-locked loop (PLL) is presented, which largely eliminates quantization noise by overclocking the delta–sigma modulator (DSM). The overclocking technique, enabled by a multipath phase detector and linear resistor-DAC (RDAC) recombination, does not require a high-reference frequency and does not require calibration. A low-power 7-nm prototype operating at 4.884 GHz exhibits 154-fs rms jitter and a figure of merit (FOM) of 255.8 dB.