Enterprise-Class Multilevel Cache Design: Low Latency, Huge Capacity, and High Reliability

The IBM Z computing platform is optimized for processing vast amounts of data and transactions with low latency in a highly virtualized and secured environment with sustained processor utilization of over 90%. The platform and its microprocessor chip are designed to deliver consistent system performance, throughput, and response times under all conditions. The innovative cache architecture of the IBM Telum Processor provides low latency, large capacity, and reliable L2 caches. Based on a novel horizontal cache persistence algorithm, these L2 caches also serves as system wide L3 and L4 caches delivering optimal enterprise application performance. When built into an IBM z16 system, these architectural features deliver 11% per-core performance improvement over the prior z15 hardware, running real-world enterprise applications.