Research and design of a bit-width adaptive convolutional neural network accelerator

Based on the ZedBoard platform, this work implements a VGG16 accelerator achieving high hardware utilization to address the need for rapid deployment of convolutional neural networks (CNNs). It encapsulates essential CNN parameters, enabling swift construction of diverse CNN models via instruction set calls. Utilizing a reconfigurable multiply-accumulate (MAC) array and dynamic bit-width scheduling, it achieves an average MAC utilization rate of 80.39% across the first 13 convolutional layers. Operating at a 150MHz core frequency, the design supports dynamic power adjustment from 1.08W (8-bit) to 2.1W (16-bit), with an average power consumption of 3.5W in adaptive mode. Measured effective throughput reaches 108.3 GOPS, yielding an energy efficiency of 30.94 GOPS/W, superior to comparable FPGA solutions. However, further improvements are possible regarding parallelism and configuration methods, particularly on the XC7Z020 platform.