15.4 Self-Enabled Write-Assist Cells for High-Density SRAM in a Resistance-Dominated Technology Node

As technology scaling increases interconnect resistance, writeability degradation in static random access memory (SRAM) becomes critical. This article presents a self-enabled write assist cell (SEWAC) that mitigates writeability degradation caused by increased bitline resistance (R ${}_{\mathrm {BL}}$ ) without requiring timing control. The SEWAC has a cell-compatible layout with the standard 6T bitcell and is directly inserted between bitcell rows without white space. SEWAC detects BL voltage transitions and self-activates to provide additional write paths, reducing the BL saturation voltage. Simulation results using a 4:1 bit-interleaved $256\times 128$ SRAM macro show that SEWAC achieves the $6\sigma $ writeability yield target for R_BL per cell (R ${}_{\mathrm {BL\_cell}}$ ) up to $120~\Omega $ . Compared to the write assist cell (W-AC) scheme, SEWAC reduces area overhead by 50% in the bit-interleaved structure while maintaining comparable writeability performance. A 28-nm test chip measurement shows that SEWAC maintains 100% writeability yield up to R ${}_{\mathrm {BL\_cell}} = 240~\Omega $ and reduces the required word-line pulsewidth (WLPW) by 33%. In addition, SEWAC demonstrates stable operation across a wide supply voltage range from 0.67 to 1.2 V, outperforming the conventional structure. The proposed SEWAC scheme also shows robustness to threshold voltage variation of the assist cells, thus making it a suitable solution for high-density, high-reliability SRAM macros in advanced technology nodes.