Hybrid Integration of Gate-All-Around Stacked Si Nanosheet FET and Si/SiGe Super-Lattice FinFET to Optimize 6T-SRAM for N3 Node and Beyond

The implementation of vertically stacked gate-all-around nanosheet FET (GAA NSFET) may help improve the performance of static random access memory (SRAM) for the design flexibility with variable NS widths. However, the method that often relies on the increasing of device width for higher driving current is to cause an increased SRAM cell area and degrade the scalability of transistor in advanced nodes. In this article, an innovated SRAM bitcell design with hybrid integration of Si NSFET and Si/SiGe super-lattice FinFET (SL-FinFET) in one SRAM cell is proposed for less area and improved performance in 3 nm and beyond nodes. Under the same footprint, p-type SL-FinFET delivers obviously enhanced driving current compared with NSFET and it may yield improved circuit performance for the SRAM cell with natural transistor ratio. The integration process method and the layout schemes for two kinds of typical 6T-SRAM cells, including the high-robustness cell (HI-R Cell) and the high-speed cell (HI-S Cell) with the hybrid integration method, are presented for optimizing high-density (HD) and high-performance (HP) SRAM. As compared with the HD NSFET SRAM cell, the HD HI-R Cell achieves 16.2% improvement in read static noise margin (RSNM) and the HD HI-S Cell achieves 21.6% reduction in read time and 28.6% reduction in write time. The HP hybrid integrated cell even pushes the SRAM cell performance arriving to the theoretical limits of regular NSFETs. Moreover, the hybrid integration scheme may provide another revolutionary method to optimize transistor ratio by adjusting the height of SiGe thickness in the transistors.