A 0.006-mm 2 0.96-LSB-INL PP 8–14-GHz 7b Twin-PI Using an Unequal-Weight Combiner With a Self-Biased-PLL Based Low-Power Compact 4-Phase Clock Generator

This brief presents a high-linearity twin phase interpolator (PI) with a self-biased PLL (SB-PLL) based low-power 4-phase clock generator. An unequal-weight integrating-mode combiner (UEQW-IMCB) is proposed to eliminate the residual nonlinearity introduced by non-ideal factors in the twin-PI. Besides, the proposed UEQW-IMCB reduces power consumption and area occupation compared with equal-weight current mode logic combiner (EQW-CMLCB) in prior twin-PI. Furthermore, a self-biased-PLL based multi-phase clock generator (MPCG) is introduced for reliable 4-phase clock generation with tiny area and low power. Fabricated in a 28-nm CMOS process, our prototype only occupies a compact core area of 0.006 mm², and achieves 0.96-LSB-INL_PP and 8-14-GHz frequency range. The total power consumption of our MPCG and twin-PI is only 16.3 mW at 14 GHz.