Investigating the Thermal Resistance of the Si and Epoxy Interface

This paper proposes a package-level method to characterize the interfacial thermal resistance (ITR) at the silicon/ epoxy (die-attach) interface using the transient thermal tester (T3Ster). This approach is first validated by extracting bulk thermal conductivity from T3Ster and comparing the values with independent Hot Disk measurements. A bilayer sample is subsequently measured at two different thicknesses; by analyzing the change in measured thermal resistance with thickness and the thermal resistance of silicon, the ITR between the layers can be derived. This method requires only a simple bilayer specimen without special structures and is applicable to process verification and material screening in electronics packaging.