2.5D PIC Photonic Interposer Engine for Next Generation Photonic Link CPO of High-Performance Computing and Data Communications

The demand of HPC (High-Performance Computing) and Data Centre with Photonic Link (Photonic Connectivity Link) and$200 \mathrm{G} /$Lane capability are growing to fulfill next generation of data transferring loading requirements. This work aims at creating a PE (Photonic Engine) with CPO (Co-Packaged-Optics) architecture capable of integrating with multiple electronic integrated circuits (EICs), photonic integrated circuits (PIC), on-chip laser sources, fiber array unit (FAU), and TSV Interposer, to enable Photonic Link to be integrated between multiple 2.5D CoWoS (Chip-on-Wafer-on-Substrate) package HPC engine