A 16Gb 12.7Gb/s/pin LPDDR5-Ultra-Pro DRAM with 4-Phase Self-Calibration and AC-Coupled Transceiver Equalization in a 5th-Generation 10nm DRAM Process

The rapid growth of AI, AR, and VR applications has increased demand for high-speed data processing and high-density low-power memory modules. LPDDR5X has played an important role in meeting these demands [1]. LPDDR5X introduced optional JEDEC features, such as per-pin decision-feedback equalizers (DFE), offset calibration, pre-emphasis transmitters, and read duty-cycle adjusters (RDCA) [2], to enhance 10 performance; however, LPDDR5X faces various speed-requirement challenges. Recently, there has been a strong demand for high-speed operation beyond 10.7Gb/s/pin; the low-power compression-attached memory module 2 (LPCAMM2) for servers has emerged to address this low-power high-capacity requirement. To achieve sufficient 10 timing margins, using lossy channels, additional transceiver techniques are required. In this paper, we present a 4-phase self-calibration technique to reduce clock phase skew further and three different AC-coupled equalization schemes to increase operating frequency. By utilizing these techniques, we have successfully validated a 16Gb LPDDR5X operating at 1.05V in a 5^th-generation 10nm DRAM technology.