MAHR: A Multi-Application Hybrid Reconfigurable Mechanism for Energy-Efficient Chiplet Interconnection Network

The use of multi-core chiplet systems is a promising technology for efficiently running large-scale hybrid applications, offering significant cost and performance advantages over the traditional 2D integrated circuits. However, incorrect task mapping and architecture design can lead to high power consumption and degraded performance. Current solutions mainly address these problems for 2D monolithic chips, which cannot be directly applied to 2.5D chiplet systems. To this end, this paper proposes a Multi-Application Hybrid Reconfigurable (MAHR) mechanism for task mapping and interconnection network construction, aiming to reduce energy consumption while optimizing communication latency. MAHR consists of three steps. In the first step, a Modified Adaptive Large Neighborhood Search (MALNS) algorithm is designed to solve the Chiplet Hybrid Applications Mapping Problem (CHAMP), allocating computational resources to application tasks; in the second step, the interconnection network is rebuilt using the results from the first step. This is accomplished through a novel reconfigurable interposer router that allows packets to bypass intermediate nodes; and in the third step, the results obtained in the second step are post-processed by checking all interposer nodes, restoring the router configurations of the nodes that have conflict links, and power-gating the unused routers. Compared to existing methods, simulation results demonstrate that MAHR reduces system power consumption and improves performance with little overhead in both synthetic and real-world scenarios. On average, MAHR achieves a 6.11% improvement in performance and an 11.3% reduction in power consumption, while increasing its area overhead by only 5.88%.