FLOORPLAN DESIGN FOR WIRING LENGTH MINIMIZATION IN ULSI CHIP USING SIMULATED ANNEALING

Floorplan and placement are very critical problems in ULSI CAD design. The common ULSI system design objectives are such as improving or maximizing wiring ability, reliability and/or yield, and reducing or minimizing chip size, power consumption, crosstalk and coupling noise. These are crucial factors in designing next generation EDA (Electronic Design Automation) tools. Semiconductor scaling limits are forcing designers to look to novel circuits and design techniques to reduce design boundaries to maintain performance growth. In this research paper, we consider two system design objectives which are wiring length and crosstalk minimization. These are needed for greater modeling complexity and accuracy in EDA (Electronic Design Automation) tools. We propose methodologies and directions for floorplan design automation tools to meet the challenges ahead with Simulated Annealing (SA) approach. This approach is one of the efficient heuristic search algorithms to effectively predict and optimize various design objectives.